VP5225 features low threshold (-2.4v max.) high input impedance low input capacitance fast switching speeds low on-resistance free from secondary breakdown low input and output leakage applications medical ultrasound imaging non-destructive evaluation solid state relays telecom switches logic level interfaces C ideal for ttl and cmos ? ? ? ? ? ? ? ? ? ? ? ? general description this low threshold, enhancement-mode (normally-off) transistor utilizes a vertical dmos structure and supertexs well-proven, silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coef?cient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. p-channel enhancement-mode vertical dmos fet absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 o c to +150 o c soldering temperature* 300 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * distance of 1.6mm from case for 10 seconds. ordering information device package option bv dss /bv dgs (v) r ds(on) (max) () i d(on) (min) (a) 3-lead to-252 (d-pak) VP5225 VP5225k4 -250 3.0 -2.5 pin con?guration 3-lead to-252 (d-pak) (k4) ga te source drain yy = year sealed ww = week sealed l = lot number yyww VP5225 llllll l product marking 3-lead to-252 (d-pak) (k4) obsolete
2 VP5225 electrical characteristics (t a = 25 o c unless otherwise speci?ed) sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage -250 - - v v gs = 0v, i d = -250a v gs(th) gate threshold voltage -1.0 - -2.4 v v gs = v ds , i d = -1.0ma v gs(th) change in v gs(th) with temperature - - 4.5 mv/ o c v gs = v ds , i d = -1.0ma i gss gate body leakage - - -100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - -10 a v gs = 0v, v ds = max rating - - -1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125c i d(on) on-state drain current -2.5 - - a v gs = -10v, v ds = -25v r ds(on) static drain-to-source on-state resistance - - 5.0 v gs = -4.5v, i d = -250ma - - 3.0 v gs = -10v, i d = -1.0a r ds(on) change in r ds(on) with temperature - - 1.7 %/ o c v gs = -10v, i d = -1.0a g fs forward transductance 500 - - mmho v ds = -25v, i d = -200ma c iss input capacitance - - 400 pf v gs = 0v, v ds = -25v, f = 1.0mhz c oss common source output capacitance - - 150 c rss reverse transfer capacitance - - 50 t d(on) turn-on delay time - - 20 ns v dd = -25v, i d = -500ma, r gen = 25 t r rise time - - 30 t d(off) turn-off delay time - - 60 t f fall time - - 30 v sd diode forward voltage drop - - -1.8 v v gs = 0v, i sd = -500ma t rr reverse recovery time - 300 - ns v gs = 0v, i sd = -500ma notes: 1. all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulsed test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. notes: ? i d (continuous) is limited by max rated t j of 150 o c. ? mounted on fr4 board, 25mm x 25mm x 1.57mm thermal characteristics package i d (continuous) ? (ma) i d (pulsed) (a) power dissipation @t a = 25 o c (w) jc ( o c/w) ja ( o c/w) i dr ? (ma) i drm (a) 3-leadto-252 (d-pak) 645 3.0 2.5 ? 6.25 50 ? 645 3.0 switching waveforms and test circuit 90% 10% 90% 90% 10% 10% puls e genera to r v dd r l outpu t d.u.t . t (on) t d(on) t (off ) t d(off) t f t r inpu t input output 0v v dd r gen 0v -10v obsolete
3 VP5225 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-VP5225 nr053008 3-lead to-252 d-pak package outline (k4) notes: 1. 4 terminal locations are shown, only 3 are functional. lead number 2 was removed. 1 2 3 4 l4 l5 b b2 e d1 e1 l1 l seating plane a1 gauge plane d e detail b front v iew side v iew rear v iew detail b 1 h c2 a l3 l2 b3 symbol a a1 b b2 b3 c2 d d1 e e1 e h l l1 l2 l3 l4 l5 1 dimension (inches) min .086 - .025 .030 .195 .018 .235 .205 .250 .170 .090 bsc .370 .055 .108 ref .020 bsc .035 - .045 0 o 0 o nom - - - - - - .240 - - - - .060 - - - - - max .094 .005 .035 .045 .215 .035 .245 - .265 - .410 .070 .050 .040 .060 10 o 15 o jedec registration to-252, variation aa, issue e, june 2004. drawings not to scale. obsolete
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